This invention relates to a mixed bipolar-MOS process for fabricating both bipolar and field effect transistors on a common integrated circuit chip.
Chip makers have long known that mixed bipolar-MOS processes, referred to in the art as BiMOS and BiCMOS, can produce faster and denser integrated circuits than can either technology alone. However, it has taken a long time to master the complex processing that these integrated circuits required. The advantages of mixed bipolar-MOS have been apparent since the early 1970's. At that time, however, bipolar and MOS structures required entirely different techniques and tools to fabricate. To design a mixed process device meant considerable expense. The present invention is a process technology that makes it very easy to fabricate mixed bipolar MOS devices in a common integrated circuit, obtaining the advantages of both bipolar and MOS processes and devices without significant additional expense.
Several integrated circuit manufacturers have been investigating methods of merging or mixing bipolar and MOS structures on the same chip and have disclosed or marketed BiMOS or BiCMOS devices. A summary of developments in this area of technology is presented in B. C. Cole, "Mixed-Process Chips Are About To Hit The Big Time," Electronics, Mar. 3, 1986, pages 27-31. This article discloses the wide range of processes that designers are trying in attempting to make satisfactory hybrid bipolar-MOS processes. Most begin with essentially a MOS process and add steps as needed to include a bipolar subprocess in the overall fabrication process. A few take the opposite approach.
A mixed bipolar-CMOS process is described, and the bipolar process is illustrated, in "A Bipolar Process That's Repelling CMOS," Electronics, Dec. 23, 1985, pages 45-47. One example of a mixed bipolar-CMOS circuit is disclosed in J. Miyamoto, et al., "A 28ns CMOS SRAM with Bipolar Sense Amplifiers," 1984 IEEE National Solid-State Circuits Conference Digest of Technical Papers, pages 224-225, 344 (1984). Mixed processes are briefly discussed, and additional references cited, in Brown, D. M., et al., "Trends in Advanced Process Technology--Submicrometer CMOS Device Design and Process Requirements," Proc. IEEE, Vol. 74, No. 12, pp. 1678-1702, Dec. 1986, at p. 1694.
The principal drawback, however, of all of these technologies has been an inability to produce very fast bipolar transistors in a mixed bipolar-MOS process. The mixed-process chips reported in the above-cited Cole article generally exhibit bipolar speeds in the range of 2-3 GHz. Only one process, of Hughes Aircraft Co.'s Semiconductor Division, is reported to produce NPN transistors with cutoff frequencies in excess of 5 GHz and PNP devices of over 2.5 GHz. The Hughes process is described as somewhat more complex and expensive than most other mixed processes, with 20 masking steps.
Another mixed process is disclosed in Ogive, K., et al., "13-ns, 500-mW, 64-kbit ECL RAM using HI-BICMOS Technology," IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, pp. 681-685, Oct. 1986, which reports a cutoff frequency of 4 GHz.
These bipolar performance characteristics would be considered rather slow in terms of the current state of bipolar-only art. Most bipolar processes in current commercial use produce bipolar speeds in the range of 5-7 GHz. Recently, a new generation of bipolar devices has emerged which exhibit speeds in the range of 9-17 GHz. All of these devices are produced by processes that are substantially more complex and critical than those used to produce mixed bipolar-MOS devices or bipolar-only devices in the 5-7 GHz range.
Advanced bipolar technologies generally use a self-aligned process technology to attain very high speed device performance. Examples of these processes are disclosed in U.S. Pat. No. 4,381,953 to Ho et al., U.S. Pat. No. 4,483,726 to Isaac et al.; T. Ning et al. "Bipolar Trends," Proc. IEEE, Vol. 74, No. 12, pp. 1669-1677, Dec. 1986; and in S. Konaka, "A 30 ps Si Bipolar IC Using Super Self-Aligned Process Technology," Extended Abstracts 16th Conference on Solid State Devices and Materials, pages 209-212 (1984). A circuit fabricated using the Konaka et al. process is disclosed in "A 9-GHz Frequency Divider Using Si Bipolar Super Self-Aligned Process Technology," IEEE Electron Device Letters, Vol. EDL-6, No. 4, pages 181-183 (Apr. 1985).
A metal-oxide-semiconductor field-effect transistor (MOSFET) of conventional form is shown in FIG. 1. The conventional p- channel MOSFET 20 comprises a substrate 22 of p+ silicon having source and drain regions 24 and 26 of n+ material formed therein immediately beneath the upper surface 28 of the substrate. The source and drain regions are bounded by field oxide layer 29, and are separated by a channel region 30, in which the p+ material of the substrate extends to the upper surface 28. A PN junction is formed between the P+ silicon and each of the N+ regions. The spacing between the source and drain regions defines a channel width of region 30. A thin layer 32 of thermally-formed or chemical vapor deposited (CVD) silicon dioxide overlies the channel region and the immediately adjacent margins of the source and drain regions 24 and 26, and a gate 34 of polysilicon overlies the layer 32. A layer 36 of CVD silicon dioxide is applied over the source and drain regions and over the gate 34. Holes 38 and 40 are formed in the layer 36 to expose the source and drain regions 24 and 26, respectively. A third hole (not shown) is formed out of the plane of the drawing so as to expose the gate 34. Metal, e.g., aluminum, is deposited over the layer 36 and enters the holes in the layer 36. The metal is selectively removed so as to form distinct source and drain contact electrodes 42 and 44 and a gate contact electrode (not shown). When the electrodes 42 and 44 are connected to ground and a positive voltage respectively, and the gate is at approximately ground or negative potential (depending on the threshold voltage V.sub.t, which may be above or below "ground"), the source and drain regions are electrically isolated by the PN junction between the drain region 26 and the channel region 30. When the voltage at the gate is increased, an inversion layer is formed in the channel region immediately beneath the gate. Electrons can flow from the source region 24 to the drain region 26 through this inversion layer.
In the conventional MOSFET shown in FIG. 1, the holes 38 and 40 are formed by a photoprocessing operation that involves aligning a mask relative to the gate 34, and the electrodes 42 and 44 make contact directly to the source and drain regions, respectively. To allow for errors in locating and aligning the mask, the source and drain regions must be made sufficiently large to ensure that the electrodes 42 and 44 will make contact to the source and drain regions. The capacitance of the PN junctions between the bulk semiconductor material and the source and drain regions, respectively, depends on the area of the interfaces between the bulk material and the source and drain regions, respectively. This area in turn depends on the area of the surface 28 exposed on each side of the gate oxide 32. To obtain high speed operation, it is necessary to minimize the capacitance of the PN junctions. Therefore, it is necessary to minimize the exposed area of the surface 28. For a given channel width, this implies that the distance between the gate oxide and the field oxide must be minimized.
C. S. Oh and C. K. Kim "A New MOSFET Structure with Self-Aligned Polysilicon Source and Drain Electrode," IEEE Electron Device Letters, Vol. EDL-5, 1984, pages 400-402, disclose a MOSFET process in which the source and drain contacts are self-aligned with the source and drain regions. The source and drain electrodes are positioned over the field oxide. Therefore, the distance between the gate oxide and the field oxide can be made much smaller than in the case of the FIG. 1 device, with the result that higher speed operation is possible.
Another MOS process having similar objects is disclosed in Huang, T. Y. et al, "A MOS Transistor with Self-Aligned Polysilicon Source-Drain," IEEE Electron Device Letters, Vol. EDL-7, No. 5, May 1986, pp. 314-316. This process inverts many of the steps of Oh and Kim. The polysilicon and overlying insulative layers are first applied. Then a reverse-gate mask and etch procedure is used to open the active channel region. A layer of gate oxide is thermally grown and a second polysilicon layer is deposited to form the gate contact.
In order to minimize the channel length (and therefore maximize the operating speed), the regions of the PN junctions that are immediately adjacent the channel region must be lightly doped. Also, to maximize the source/drain breakdown voltage of a MOSFET, it is desirable that the drain region be lightly doped immediately adjacent the channel region. The source region and the major part of the drain region should be more heavily doped to minimize the source/drain resistance when the MOSFET is in its conductive state. Thus, the drain region is preferably formed in two zones: a lightly doped zone that extends at least partially under the gate, and a more heavily doped zone that connects the lightly doped zone to the drain electrode.
A known method of providing different doping levels within the drain region of a MOSFET is illustrated in FIG. 2. As shown in FIG. 2(a), the gate structure 32/34 is formed on the substrate 22. Then, a first ion implantation operation is carried out, providing a relatively low concentration of charge carriers in regions 40 on each side of the gate structure. A silicon dioxide layer 44 of uniform thickness is deposited over the gate structure and the adjacent areas of the upper surface of the substrate (FIG. 2(b)). The silicon dioxide of the layer 44 is selectively removed by reactive ion etching to a depth equal to the thickness of the layer 44, so as to expose substrate surface 28 but leave walls 46 extending along the sides of the gate structure 32/34 (FIG. 2(c)). A second ion implantation is then carried out, providing a higher concentration of charge carriers, sidewalls 46 acting as an implantation mask. Therefore, the source and drain regions each have two zones 48 and 50, of high and low conductivity, respectively. For ease of processing, the same operations are carried out on both sides of the gate.
The method described by Oh and Kim does not lend itself to the establishment of different doping levels within the drain region. Nor does the process of Huang et al. Processes disclosed in D. M. Brown et al., supra, p. 1682, FIG. 7, and p. 1690, FIG. 22, can produce such different doping levels, but employ metal source and drain contacts to the silicon substrate and added process steps.
In S. S. Wong et al., "Elevated Source/Drain MOSFET," IEDM Tech. Dig., 1984, pages 634-637, there is described a method for providing a high conductivity layer over the source and drain regions of a MOSFET by forming an epitaxial layer of silicon over the source and drain regions, but not over the gate structure, and implanting ions into the epitaxial layer and the gate structure. However, this method is subject to a disadvantage in that deposition of an epitaxial layer is normally carried out at high temperature, and high temperature processing is considered undesirable in fabrication of a MOSFET having a lightly-doped drain.
S. S. Wong, "Contact Technologies for Submicron CMOS," Cornell Program on Submicrometer Structures, 1985, discusses the use of a metal silicide contact layer over the source and drain regions to minimize the source/drain resistance. The silicide layer is formed by first depositing a layer of polysilicon over the source and drain regions and then depositing of a layer of refractory metal over the polysilicon. The device is then annealed, and the metal silicide layer is formed.
It is also known to use an oxide sidewall structure in making bipolar transistors, to define a spacing between polysilicon emitter and base contacts. This is shown by S. F. Chu et al. in "A Self-Aligned Bipolar Transistor," VLSI Science and Technology/1982 Proceedings Vol. 82-7, pp. 306-314. The process shown also uses successive implant and diffusion steps to form the intrinsic base and emitter from the layer of polysilicon forming the emitter contact. This procedure is detailed in another paper in the same Proceedings, presented by F. Barson et al., entitled "Shallow Bipolar Transistor Profiles by Diffusion from Implanted Polysilicon," pp. 282-287. It produces a very high speed bipolar transistor, with a cutoff frequency demonstrated to be as high as 15 GHz, but no way is suggested that makes this high speed available together with the high density and low power consumption of CMOS.
A need remains for a process that overcomes the drawbacks of the foregoing MOS and bipolar processes. Additionally, it would be desirable to have a process that can readily be used to produce mixed bipolar-MOS circuit.